1. Field of the Invention
The present invention relates generally to a temperature characteristic compensation circuit (or a temperature compensation circuit) capable of compensating the temperature characteristic of electric circuits such as various types of sensors.
2. Description of the Related Art
There is a conventional temperature characteristic compensation circuit (hereinafter referred to as “temperature compensation circuit”) configured to compensate the temperature characteristic of a sensor. A semiconductor integrated circuit equipped with such a temperature compensation circuit has been widely used, which is capable of receiving a signal transferred from such a sensor, and amplifies the received signal, and outputs the amplified one to various electric circuits. For example, the Japanese laid open publication number JP 2003-110367 has disclosed such a semiconductor integrated circuit equipped with a temperature compensation circuit.
FIG. 5 is a block diagram showing a configuration of the semiconductor integrated circuit equipped with the temperature compensation circuit for such a sensor.
As shown in FIG. 5, the semiconductor integrated circuit consists of a sensor element 20, an amplifier 30, an offset compensation circuit 40, a temperature compensation circuit 50 for temperature characteristic offset, a control circuit 60, a memory circuit 70, and a driver circuit 80. The sensor element 20 consists of a bridge circuit (not shown) having plural resistance elements. The amplifier 30 receives a detection signal transferred from the bridge circuit (not shown) in the sensor element 20 and amplifies the received detection signal. The offset compensation circuit 40 compensates an offset generated by variation in resistance of each resistance element forming the bridge circuit. The temperature compensation circuit 50 for temperature characteristic offset is configured to compensate offset generated by variation of temperature characteristic of each resistance element in the sensor element. The control circuit 60 controls so that the memory circuit 70 stores digital data for compensation according to a control signal transferred from the outside of the semiconductor integrated circuit. The memory circuit 70 stores digital data for use in both the offset compensation circuit 40 and the temperature compensation circuit 50 for temperature characteristic offset. The drive circuit 80 drives a current flowing through the sensor element 20.
The offset temperature compensation circuit 40 outputs to the amplifier 30 a voltage for compensating the offset of the bridge circuit in the sensor element 20 according to the digital data for various offset compensations stored in the memory circuit 70.
The temperature compensation circuit 50 outputs to the amplifier 30 a voltage for compensating the temperature characteristic offset of the bridge circuit in the sensor element 20 according to the digital data for compensating the temperature characteristic offset stored in the memory circuit 70.
The amplifier 30 amplifies the detection signal transferred from the sensor element 20 while suppressing the influence of both the offset and the temperature characteristic offset that are amplified according to the voltages supplied from both the offset temperature compensation circuit 40 and the temperature compensation circuit 50.
The semiconductor integrated circuit shown in FIG. 5 has both the offset compensation circuit 40 and the temperature compensation circuit 50 in order to perform the different adjustments of the offset compensation and the compensation for the temperature characteristic offset based on the digital data stored in the memory circuit 70.
FIG. 6 is a circuit diagram showing a configuration of the conventional offset temperature compensation circuit 50 incorporated in the semiconductor integrated circuit shown in FIG. 5.
The offset temperature compensation circuit 50 comprises a R-2R ladder resistance group made of resistances 51a to 51g, a base resistance 54, resistances 52, 53, and 57 to 59, and operational amplifiers 55 and 56. The base resistance 54 is made of a thermal sensitive resistance capable of changing its resistance value according to a temperature change.
FIG. 7A shows a temperature characteristic of a voltage V1 at an output terminal of the operational amplifier 55. FIG. 7B shows a temperature characteristic of a voltage V2 at an output terminal of the operational amplifier 56. FIG. 7C shows a temperature characteristic of a voltage (as a voltage of a compensation signal) V3 at a connection node between the resistances 58 and 59.
The entire resistance value of the R-R2 ladder resistance group composed of the resistances 51a to 51g is changed according to digital data (from the Least Significant Bit (LSB) to the Most Significant Bit (MSB)) stored in the memory circuit 70. Because the operational amplifier 55 is configured as a voltage follower, the voltage V1 at the output terminal of the operational amplifier 55 is changed according to the value of the digital data obtained from the memory circuit 70.
As a concrete example, FIG. 7A shows that the voltage V1 at the output terminal of the operational amplifier 55 increases according to the high digital data, and on the contrary, decreases according to the low digital data.
The current I that flows through the base resistance 54 can be expressed by the following equation (1).I=(V1−V0)/R1 (RT)   (1),where V0 is a divided voltage of a power source voltage Vcc by the resistances 52 and 53, and R1 (RT) is a resistance value of the base resistance 54 at a room temperature.
Because the current that flows through the resistance 57 becomes equal to the current I flowing through the base resistance 54, the voltage Δ V between the both ends of the resistance 57 can be expressed by the following equation (2).Δ V=R1×I=R1(V1−V0)/R1 (RT)   (2),where R1 is the value if the resistance 57.
The voltage V2 at the output terminal of the operational amplifier 56 can be expressed by the following equation (3).V2=V0−Δ V=V0−R1(V1−V0)/R1 (RT)   (3).
When the digital data is a high value and the voltage V1 at the output terminal of the operational amplifier 55 is greater than the voltage V0, the value Δ V becomes a positive value and the voltage V2 at the output terminal of the operational amplifier 56 becomes low relatively. The absolute value of the voltage Δ V becomes low because the resistance R1 (RT) of the operational amplifier 56 is increased according to the temperature rise. Accordingly, the voltage V2 at the output terminal of the operational amplifier 56 has the characteristic indicated by the low digital data shown in FIG. 7B.
The voltage V3, namely the voltage of compensation signal, at the connection node between the resistances 58 and 59 takes the medium digital data between the voltage V2 and the voltage V1. Accordingly, the voltage V3 takes the different voltage characteristics according to the digital data at the temperature other than the room temperature. At the room temperature, the voltage V3 takes a constant voltage characteristic shown in FIG. 7C.
The amplifier 30 performs the compensation for the temperature characteristic offset of the sensor element 20 using the compensation signal voltage V3 which takes the different voltage characteristic according to the value of the digital data.
Because each resistance forming the sensor element 20 has a different temperature characteristic, namely, each sensor element 20 takes a different temperature characteristic, it is necessary to adjust the temperature characteristic offset per sensor element 20. Therefore this adjustment needs re-writing the compensation data (digital data) into the memory circuit 70 for each sensor element 20 while monitoring the voltage of the compensation signal in order to obtain the optimum compensation data.
However, a response delay occurs in each of the operational amplifiers 55 and 56 forming the temperature compensation circuit 50 mounted on the conventional semiconductor integrated circuit, and the response delay further causes the entire operation delay. As a result, it takes much time to perform the adjustment and to obtain the optimum compensation data.